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    MIPI Alliance Blog:

    The Wires Behind Wireless

    Updates Released for MIPI STP and Other Debug and Trace Specifications

    Reliance on legacy methods of probing buses and signals with dedicated, proprietary debug and test equipment across layers can be impractical. It's often too disjointed, too complex and too costly—particularly with so many different components working together across today’s systems for mobile, IoT, automotive, industrial, 5G and other ecosystems.

    To solve this, the MIPI Debug Working Group develops low-cost and interoperable hardware and software interface and protocol specifications that work together across the full stack, leveraging functional interfaces as often as possible to improve the applicability of designers’ existing toolsets and hold down costs. Updates to four of these specifications have been recently released. 

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    Tags: Debug, Trace, MIPI Debug for I3C, MIPI STP, MIPI PTI, MIPI NIDnT

    Latest IoT Kits with MIPI Camera, Display, I3C and JEDEC UFS Give Developers a Fast Track For Designs

    It's been more than 12 months since we published our last blog post highlighting popular IoT developer kits that support MIPI camera and display interfaces. Since then, a number of new kits have been launched that support other MIPI interfaces, including MIPI I3C® (the successor to the I2C interface) and JEDEC Universal Flash Storage (which leverages MIPI M-PHY® and MIPI UniPro®), in addition to the already widely adopted MIPI CSI-2® camera and MIPI DSI®/DSI-2 display interfaces.  

    This blog highlights some of the notable kits new to the market over the last year (and one particular kit missing from the previous post). I’ll explain which MIPI interfaces they support and describe how the use of these interfaces can benefit the IoT developer community.

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    Tags: Camera, Display, MIPI Debug for I3C, IoT

    MIPI I3C and I3C Basic v1.1.1 – A Conversation with Tim McKee

    The MIPI I3C® and I3C BasicSM specifications define scalable, medium-speed, utility and control bus interfaces for streamlined, cost-efficient connection of peripheral devices and sensors with application processors. As the broadly welcomed successor to the I2C interface, MIPI I3C and its features can be used to create innovative designs for products including smartphones, wearables and systems in automobiles and server environments. 

    MIPI Alliance recently released version 1.1.1 of both the MIPI I3C and I3C Basic specifications, so we asked Tim McKee, chair of the MIPI I3C Working Group, to provide an update on what’s new with the interfaces, how they’ve evolved and where the specifications may be headed next.

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    Tags: MIPI Debug for I3C

    MIPI Alliance Releases Enhanced I3C Host Controller Interface

    The new MIPI I3C Host Controller Interface (MIPI I3C HCI℠) v1.1 specification was recently released to MIPI Alliance members as well as nonmembers, with new functionality that facilitates broader use of the MIPI I3C® interface and helps developers and the open source community integrate the latest I3C-based peripheral components into their designs.

    In this blog post, we recap the benefits of the I3C interface, explain how the HCI specification helps developers and provide an overview of the updates in this latest version.

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    Tags: Software, MIPI Debug for I3C

    MIPI Webinar to Explore Benefits, Features of New Debug for I3C Interface

    Next week, MIPI Debug Working Group Chair Enrico Carrieri and working group member Matthew Schnoor will take an in-depth look at the recently released MIPI Debug for I3CSM v1.0, which allows system designers to dynamically debug and test application processors, power management integrated circuits, modems and other power-managed components.

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    Tags: Debug, MIPI Debug for I3C

    MIPI I3C Basic in JEDEC DDR5: A Sum Greater Than Its Parts

    JEDEC Solid State Technology Association (JEDEC) and MIPI Alliance have enjoyed a long liaison relationship of collaboration, as the two organizations serve some similar but also different applications and ecosystems. When we work together closely—as in development of JEDEC’s newly announced JESD79-5 DDR5 (Double Date Rate 5) standard—it results in better outcomes and broader market opportunities for all of our combined stakeholders.

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    Tags: JEDEC, MIPI Debug for I3C
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