To transport debug controls and data between a debug and test system and a target system
MIPI Debug for I3CSM is a bare-metal, minimal-pin interface for transporting debug controls and data between a debug and test system (DTS) and a target system (TS). The specification uniquely handles the network topology in a dynamic fashion, making it perfectly suited as a flexible and scalable debug and test specification for systems that enable mobile, the Internet of Things (IoT), automotive and other use cases.
MIPI Debug for I3C allows system designers to efficiently and dynamically debug and test application processors, power management integrated circuits, modems and other power-managed components across a system of any size via the low-bandwidth MIPI I3C® interface, which requires a minimal set of pins.
The interface delivers multi-component connectivity across either dedicated debug or shared bus topologies, requires only two wires, supports multiple entry points, and maintains a network even as components power down and off a network and then rejoin after powering back up.
MIPI Debug for I3C developed by the MIPI Debug Working Group.
All MIPI debug and trace specifications, including MIPI Debug for I3C, are available for download and use by the public and the open source community. To learn more about MIPI Debug specifications, please visit the Debug section of the MIPI website. Members of the MIPI Alliance enjoy benefits including access to relevant licenses and opportunities to participate in development activities, interoperability workshops and other events.
For information about MIPI Alliance membership, visit Join MIPI.